The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
High voltage electrical transmission and distribution may be performed with a variety of configurations, including a radial system and a mesh system. A meshed grid network may have various benefits over a radial system, including higher reliability, especially under contingency conditions. However, unless the meshed grid network is able to be controlled effectively, the network may be unable to handle congestion of key transmission lines when distributed, unscheduled, or intermittent alternative energy sources are connected to the grid.
For example only, wind and solar power may be unscheduled, intermittent, and geographically distributed. Not only does this lead to inefficient operation of energy markets, but the first transmission line in a mesh network to reach its capacity may limit the capacity of the entire system, even if the majority of the lines in the system are significantly below their limits.
Unified power flow controllers (UPFCs) may mitigate this problem by balancing the load of various lines, allowing the overall system to operate closer to its theoretical maximum capacity. UPFCs may be used to implement the functionality of flexible AC transmission system (FACTS) devices, such as a static var generator (SVG), a static synchronous compensator (STATCOM), or a static var compensator (SVC). In various implementations, UPFCs may also implement power line conditioning, series compensation, phase shifting, voltage balancing, etc.
However, traditional UPFCs are built using back-to-back inverters and require bulky and complicated zigzag transformers to achieve high voltage and power handling capabilities. The zigzag transformers are very expensive (for example, 30-40% of total system costs), lossy (for example, accounting for 50% of the total power losses), bulky (for example, 40% of system area), and more prone to failure. In addition, transformers used in these applications are slow in dynamic response, sometimes taking on the order of minutes to respond due to large time constants of magnetizing inductance over resistance. In addition, transformers may pose control challenges due to transformer saturation, DC offset, and voltage surge. For this reason, traditional UPFCs have not been widely used for power control, including in alternative energy applications.
To reduce the size of the required transformers, various techniques have been used, including cascade multilevel inverters (CMIs). For example only, see Peng et al., U.S. Pat. No. 5,642,275, issued Jun. 24, 1997, the entire disclosure of which is hereby incorporated by reference. Using CMIs to create a UPFC has traditionally still required isolation transformers, even if the zigzag transformers could be reduced or eliminated.
Referring now to FIG. 1A, an example cascade multilevel inverter (CMI) 100 is presented. The CMI 100 includes bridge modules 104-1, 104-2, 104-3, and 104-4 (collectively, bridge modules 104). The bridge modules 104 are connected in series such that a second terminal of the bridge module 104-1 is connected to a first terminal of the bridge module 104-2, a second terminal of the bridge module 104-2 is connected to a first terminal of the bridge module 104-3, and a second terminal of the bridge module 104-3 is connected to a first terminal of the bridge module 104-4. A first terminal of the bridge module 104-1 and a second terminal of the bridge module 104-4 serve as terminals of the CMI 100. Each of the bridge modules 104 has third and fourth terminals to connect to a corresponding capacitor. In various implementations, an inductor is connected in series with the bridge modules 104, which may reduce transient and/or circulating current.
The bridge modules 104 are therefore associated with capacitors 108-1, 108-2, 108-3, and 108-4, respectively. The first and second terminals of the bridge modules 104 may be referred to as AC (alternating current) terminals, while the third and fourth terminals of the bridge modules 104 may be referred to as DC (direct current) terminals.
Referring now to FIGS. 1B-1E, example implementations of bridge modules, such as the bridge modules 104 of FIG. 1A, are shown. In FIG. 1B, a bridge module 400 includes a first terminal connected to a node between a switch 404 and a switch 408. A second terminal of the bridge module 400 is connected to a node between a switch 412 and a switch 416. Opposite ends of the switches 404 and 412 are connected to a first terminal of a capacitor 420. Opposite terminals of the switches 408 and 416 are connected to a second terminal of the capacitor 420. The arrangement of the switches 404, 408, 412, and 416 may be referred to as a full bridge.
Referring now to FIG. 1C, an alternative implementation of the bridge module 440 is shown. A first terminal of the bridge module 440 is connected to a node in between a switch 444 and a first terminal of a capacitor 448. A second terminal of the bridge module 440 is connected to a node between the switch 444 and a switch 452. An opposite terminal of the switch 452 is connected to a second terminal of the capacitor 448. The arrangement of the switches in FIGS. 1C-1E may be described as half bridges generally and respectively as positive, negative, and neutral half bridges.
Referring now to FIG. 1D, another example half-bridge implementation of a bridge module 480 is shown. A first terminal of the bridge module 480 is connected to a node between a switch 484 and a switch 492. Opposite terminals of the switches 484 and 492 are connected to first and second terminals of a capacitor 496, respectively. A second terminal of the bridge module 480 is connected to a node between the switch 492 and the second terminal of the capacitor 496.
Referring now to FIG. 1E, another example half-bridge implementation of a bridge module 520 is shown. A first terminal of the bridge module 520 is connected to a node between a switch 524 and a switch 528. A second terminal of the bridge module 520 is connected to a second terminal of a capacitor 532 and a first terminal of a capacitor 536. An opposite terminal of the switch 524 is connected to a first terminal of the capacitor 532, while an opposite terminal of the switch 528 is connected to a second terminal of the capacitor 536.
Each of the bridge modules 400, 440, 480, and 520 can present a selectable voltage between its terminals. For example, the voltage between the terminals of the bridge module 400 can be VDC, zero, or −VDC, where VDC is the voltage across the capacitor 420. The voltage between the terminals of the bridge module 440 or the bridge module 480 can be either VDC or 0. The voltage between the terminals of the bridge module 520 can either be VDC1 or VDC2, where VDC1 is the voltage across the capacitor 532 and VDC2 is the voltage across the capacitor 536.
Referring now to FIG. 1F, an example implementation of a switch 560 is presented. The switch 560 may be used as one or more of the switches in any of FIGS. 1B-1E. The switch 560 has a first terminal and a second terminal and a semiconductor switching device 564 connected between the first and second terminals. A diode 568 is connected antiparallel to the semiconductor switching device 564. In various implementations, the semiconductor switching device 564 may include, for example only, a power MOSFET (metal-oxide-semiconductor field-effect transistor), an IGBT (insulated gate bipolar transistor), or a gate turn-off thyristor.
Referring now to FIG. 1G, another example implementation of a switch 580 is presented, which may be used as one or more of the switches in any of FIGS. 1B-1E. The switch 580 includes a semiconductor switching device 584 and a diode 588 connected antiparallel to the semiconductor switching device 584. The semiconductor switching device 584 may be implemented using, for example, an insulated gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor (MOSFETs), and/or a gate turn-off thyristor.
Referring now to FIG. 2A, an example three-phase three-wire connection of CMIs in a delta configuration is presented. In this case, CMI 160, CMI 162, and CMI 164 are connected in a delta configuration in which a second terminal of the CMI 160 is connected to a first terminal of CMI 162, a second terminal of the CMI 162 is connected to a first terminal of the CMI 164, and a second terminal of the CMI 164 is connected to a first terminal of the CMI 160. The incoming three-phase voltages, VA, VB, and VC, are connected to the first terminals of the respective CMIs 160, 162, and 164.
Referring now to FIG. 2B, an example three-phase three-wire connection of CMIs in a wye (or, star) configuration is presented. For simplicity, the same three CMIs 160, 162, and 164 are shown, and still receive voltages VA, VB, and VC at the respective first terminals. In this case, however, the second terminals of the CMIs 160, 162, and 164 are connected together at a common node.